As it is known, phase change memories, the so-called ePCMs (embedded Phase Change Memories) are a new generation of integrated non-volatile memories, in which, to store information, the characteristics of materials having the property of switching between phases having different electrical characteristics are exploited. These materials may switch between an amorphous, disorderly, phase and a crystalline or polycrystalline, orderly, phase and resistivities of considerably different value, and consequently a different value of a datum stored, are associated with the two phases. For example, the elements of the VI group of the periodic table, such as tellurium (Te), selenium (Se), or antimony (Sb), referred to as chalcogenides or chalcogenic materials, may be advantageously used for manufacturing phase change memory cells; in particular, an alloy made up of germanium (Ge), antimony (Sb), and tellurium (Te), known as GST (having the chemical composition Ge2Sb2Te5) is currently widely used in such memory cells.
The phase changes may be obtained by locally increasing the temperature of the cells of chalcogenic material, through resistive electrodes (generally known as heaters) set in contact with respective regions of chalcogenic material.
Access (or selection) devices (for example, MOSFETs), are connected to the heaters and selectively enable passage of a programming electric current therethrough; this electric current, by the Joule effect, generates the temperatures required for the phase change.
In particular, when the chalcogenic material is in the amorphous state, at a high resistivity (the so-called RESET state), it is required to apply a current/voltage pulse (or a suitable number of current/voltage pulses) of duration and amplitude such as to enable the chalcogenic material to cool slowly. Subjected to this treatment, the chalcogenic material changes its state and switches from the high-resistivity state to a low-resistivity state (the so-called SET state). Vice versa, when the chalcogenic material is in the SET state, it is required to apply a current/voltage pulse having suitable duration and high amplitude, so as to cause the chalcogenic material to return into the high-resistivity amorphous RESET state.
During reading, the state of the chalcogenic material is detected by applying a voltage sufficiently low as not to cause a sensible heating thereof, and then reading the value of the current that flows in the memory cell via a suitable sense amplifier. Since the current is proportional to the conductivity of the chalcogenic material, it is possible to determine in which state the material is, and consequently to determine the datum stored in the memory cell.
In general, a PCM device allows to achieve important advantages, among which are high scalability and reading speed combined with a reduced current consumption and a high efficiency. As shown schematically in FIG. 1, a non-volatile PCM device, designated by 1, generally comprises a memory array 2 made up of a plurality of memory cells 3, arranged in rows or wordlines, WL, and bitlines, BL.
Each memory cell 3 is constituted by a storage element 3a and by an access element 3b, which are connected in series between a respective bitline BL and a terminal at reference potential (for example, ground, GND). A wordline WL is defined by the set of all the control terminals of the access elements 3b aligned along one and the same row.
The storage element 3a includes a phase change material element (for example, a chalcogenide, such as GST), and is consequently able to store data in the form of resistance levels associated with the different phases assumed by the same material (for this reason, in the attached figures it will at times be modeled as a resistor with variable resistance). The access element 3b, as in the embodiment illustrated, is an N-channel CMOS transistor having its gate terminal connected to a respective wordline WL, its drain terminal connected to the storage element 3a, and its source terminal connected to the reference potential terminal. The access element 3b is controlled and biased so as to enable, when selected, the passage of a reading, or programming, current through the storage element 3a, having suitable values during respective reading or programming operations.
A column decoder 4 and a row decoder 5 enable selection of the memory cells 3, on the basis of address signals received at input (generated in a known way and designated as a whole by AS) and more or less complex decoding schemes, and in particular selection of the corresponding wordlines WL and bitlines BL, each time addressed, enabling biasing thereof at suitable voltage and current values. In particular, it is known that SET and RESET programming operations may be executed on “words” including a number Nb of bits and respective memory cells 3 (Nb being an integer number higher or equal to 1), i.e. on a corresponding number Nb of bitlines BL in a wordline WL.
Column decoder 4 is thus designed to select for programming a “column”, that is as a group of bitlines BL, in a number Nb corresponding to the number of bits of the word to be programmed (bitlines EL, one per memory cell 3, are selected at the same time by the column decoder 4). In the following, the term “column” will therefore be intended to refer to a group of Nb bitlines BL.
It is also known that during writing (or programming) operations, both when programming of the SET state is required and when programming of the RESET state of the chalcogenide material of the memory cells 3 is required, supplying to the storage elements 3a of high-value current pulses is needed, for activation of the mechanisms for change of state. For example, programming of the SET state may be obtained via a box or rectangular current pulse having an amplitude for example between 100 μA and 200 μA, such as 140 μA, whereas programming of the RESET state may be obtained via a box or rectangular current pulse having a higher amplitude for example between 200 μA and 700 μA, such as 300 μA.
The voltage on the bitline BL selected for programming BL may be expressed via the following relation:VBL=RGST·I+Vh+VDS 
where RGST is the resistance value of the storage element 3a, I is the current circulating through it, Vh is the so called “holding voltage”, having a value which is characteristic for the PCM memory cell, and VDS is the voltage drop between the drain and source terminals of the access element 3b. 
Considering a value of the resistance RGST of approximately 2.5 kΩ, a value of 0.5 V for the holding voltage Vh, and a voltage drop VDS between 1 V and 1.5 V, the voltage on the bitline VBL may reach values in the region of 3 V. It follows that the voltage supplied to the column decoder 4 must be higher than this value, for example equal to 3.6 V, in order to enable the passage of the desired current during the programming step.
The column decoder 4 is moreover configured for internally providing two distinct paths towards the bitlines BL of the memory array 2 each time selected: a reading path, designed to selectively create a conductive path between each selected bitline BL and a sense-amplifier stage 7, configured to compare the current circulating in the addressed memory cell 3 with a reference current in order to determine the datum stored; and a programming path, designed to selectively create a conductive path between each selected bitline BL and a driving stage 8, configured to supply the high currents required for the programming operations of the SET and RESET states.
For this purpose, the column decoder 4 comprises, for each reading and programming path, suitable selection elements, in particular controlled transistors, connected in cascaded fashion and configured for implementing a hierarchical address decoding for selection of the memory cells 3.
In particular, as shown schematically in FIG. 2, the memory array 2 is generally arranged in a plurality of sectors, each of which comprises a plurality of memory cells 3. Each sector has a plurality of wordlines WL and respective local bitlines, designated once again by BL (distinct from those of the other sectors), which are physically connected to the memory cells 3 of the memory array 2 present in the same sector. In addition, for each set of local bitlines BL, for example four in number, two main bitlines MBL are provided, one for reading, designated by MBLr, and one for programming, designated by MBLp, designed, when selected at a higher hierarchical level, to enable subsequent selection, at a lower hierarchical level, of one or more of the respective local bitlines BL and of the corresponding memory cells 3. The main bitlines MBL traverse a number of sectors and may be selected in groups at a hierarchical decoding level still higher than the one associated with selection of the main bitlines MBL.
The column decoder 4 hence comprises: for each sector, at least one respective first-level decoding circuit for the reading operations and for the (SET and RESET) programming operations, coupled to, and operable for selecting, the respective local bitlines BL; and moreover, for each group of sectors, a respective second-level decoding circuit, once again for the reading operations and for the programming operations, coupled to, and operable for selecting, the respective main bitlines MBL (as previously highlighted, also a decoding circuit at a still higher level, for selection in groups of the main bitlines MBL, may possibly be provided).
In a known manner, the decoding circuits for the reading operations are provided with N-channel CMOS transistors, whereas the decoding circuits for the programming operations are provided with P-channel CMOS transistors.
Patent application US 2013/0258766 A1, in the name of the present Assignee, discloses a decoding architecture for a PCM device, which allows use of MOS transistors of the low-voltage type only, due to: the use of transistor protection elements, in cascode configuration; the definition of suitable conditions of dynamic biasing during memory operations, both for the wordlines WL and the bitlines BL; and a suitable timing of the same biasing conditions during successive biasing steps required in preparation for the various operations of reading and/or programming of the memory device.
In this regard, it is known, for example, that using the 90-nm CMOS technology it is possible to provide: low-voltage transistors (for example, ones using voltages ranging between 1.08 V and 1.32 V, equal to a logic voltage Vdd of the memory device 1, and able to withstand, for a short period of time, also operating voltages of slightly higher values, for example equal to 1.8 V), having a smaller thickness of the gate oxide and a smaller occupation of area; and high-voltage transistors, i.e., ones designed to withstand higher operating voltages, with a maximum value, for example, between 1.55 V and 5.5 V, i.e., of a value higher or much higher than the logic voltage Vdd, and having a large thickness of the gate oxide and high occupation of area.
In more details, and with reference to FIG. 3, this decoding architecture, designated as a whole by 10, for the memory device, designated once again by 1 (and whereof only one memory cell 3 and wordline WL of the memory array 2 is shown for sake of simplicity), comprises: a column decoder, once again designated by 4, which includes two distinct decoding paths, one for the reading operations and one for the programming operations, and in particular a reading decoding circuit 4a and a programming decoding circuit 4b; and a row decoder, once again designated by 5.
In detail, each reading and programming decoding circuit 4a, 4b of the column decoder 4 comprises:
a respective selection stage 15a, 15b; and
a respective biasing stage 16a, 16b, operatively coupled to the respective selection stage 15a, 15b so as to supply the suitable biasing quantities for selection and biasing of the bitlines of the memory array 2.
Each selection stage 15a, 15b comprises: a plurality of selection switches that are hierarchically arranged on a number of decoding levels, in particular at least one first decoding level and one second decoding level, and that can be selectively operated in cascaded fashion so as to create a conductive path between the selected bitlines and a sense-amplifier stage, once again designated by 7, designed to compare the current circulating in the addressed memory cells 3 with a reference current to determine the datum stored, or, respectively, between the selected bitlines and a driving stage 8, configured to supply the high currents required for the programming operations of the SET and RESET states.
In greater detail, each selection stage 15a, 15b comprises at least:
a plurality of first-level selection switches (in FIG. 3 only one is shown, for simplicity of illustration), namely, NMOS transistors, designated by MN1, in the case of the reading decoding circuit 4a, and PMOS transistors, designated by MP1, in the case of the programming decoding circuit 4b, connected to one another in parallel and each between a respective main, or global, bitline MBL (designated once again by MBLr for the reading path and MBLp for the programming path) of the memory array 2 and a respective internal node N1, these transistors being operable for enabling selection and biasing of a respective local bitline BL and its connection to the respective main bitline MBL (according to a hierarchical decoding scheme of a known type, here not described in detail); and
a plurality of second-level selection switches (in FIG. 3 once again only one is shown, for simplicity of illustration), namely, NMOS transistors, designated by MN2, in the case of the reading decoding circuit 4a, and PMOS transistors, designated by MP2, in the case of the programming decoding circuit 4b, connected to one another in parallel and each between a respective internal node N2 and a respective main bitline MBL of the memory array 2, these transistors being operable for enabling selection and biasing of the respective main bitlines MBL (according to a hierarchical decoding scheme of a known type, here consequently not described in detail).
As it is known, the number of the first-level and second-level selection switches MN1, MP1, MN2, MP2 depends on the organization and dimensions of the memory array 2 and on the corresponding division into sectors.
Moreover, in the case illustrated, the internal node N2 is directly connected to: the sense-amplifier stage 7, in the case of the reading decoding circuit 4a, for supplying thereto a reading current Ir, having a value that is a function of the datum stored in the memory cell 3 in the reading step; or the driving stage 8, in the case of the programming decoding circuit 4b, for receiving therefrom a driving current Ip, of an appropriate value (for example, 300 μA, in the case of a programming operation of a RESET state).
Alternatively, each selection stage 15a, 15b may comprise at least one further hierarchical decoding level, and in particular a plurality of third-level selection switches, which will be designated hereinafter by MN3, MP3, in analogy with what has been already described, set between the respective second internal node N2 and the sense-amplifier stage 7 or the driving stage 8.
Each selection stage 15a, 15b further comprises a plurality of protection elements, namely, NMOS transistors, designated by MNC, in the case of the reading decoding circuit 4a, and PMOS transistors, designated by MPC, in the case of the programming decoding circuit 4b, connected in cascade configuration, with respect to a respective first-level selection switch MN1, MP1, between a respective internal node N1 and a respective local bitline EL of the memory array 2. The protection elements MNC, MPC may be suitably operated for protecting the selection switches at the various decoding levels, when selected and connected in cascaded fashion. The protection elements MNC, MPC may for this purpose be biased so as to contribute to the fact that, between the conduction and control terminals of the selection switches, voltage differences never occur, higher than a maximum voltage withstandable by the low-voltage transistors for short time intervals, which are precisely those required by the programming operations (for example, having a value of 1.8 V, slightly higher than the logic voltage Vdd).
Moreover, the selection stage 15b of the biasing decoding circuit 4b comprises a well-biasing terminal 18, electrically connected to which are the well regions (having a doping of an N type) of the various PMOS transistors that constitute at least the first-level and second-level selection switches MP1, MP2 and moreover the protection elements MPC.
Each biasing stage 16a, 16b of the column decoder 4 in turn comprises:
a first-level biasing unit 19a, 19b, configured to supply suitable first-level biasing signals, designated by YON and YOP, to the control terminals of the first-level selection switches MN1, MP1 for selectively controlling closing and opening thereof;
a second-level biasing unit 20a, 20b, configured to supply suitable second-level biasing signals, designated by YN and YP, to the control terminals of the second-level selection switches MN2, MP2 for selectively controlling closing and opening thereof; and
a protection biasing unit 21a, 21b, configured to supply suitable biasing signals, designated by YNC and YPC, to the control terminals of the protection elements MNC, MPC.
In addition, the biasing stage 16b of the programming decoding circuit 4b comprises a well-biasing unit 22, configured to supply suitable biasing signals to the well-biasing terminal 18.
The row decoder 5 in turn comprises a row-biasing unit 24, configured to supply appropriate biasing signals, designated by VWL, to the wordlines WL of the memory array 2, and consequently to the respective control terminals of the access elements 3b of the memory cells 3.
Based on address signals AS received at input, indicative of the bitlines and wordlines that have to be addressed for the operations of reading or programming of the corresponding memory cells 3, the biasing stages 16a, 16b of the column decoder 4 and the row-biasing unit 24 of the row decoder 5 are controlled so that they will select and supply the appropriate biasing quantities to the respective selection and access elements in order to set up the required reading and programming conductive paths towards the memory cells 3.
In particular, suitable biasing steps that are temporally consecutive and preliminary to the effective reading/programming operations are executed; these preparation steps are distinguished by respective biasing conditions.
As discussed in detail in the above patent application, these biasing conditions are designed for preventing that between the conduction and control terminals of the various low-voltage transistors in the decoding architecture 10 voltage differences occur, being higher than a maximum withstandable voltage (for example, a voltage slightly higher than the logic voltage Vdd), in any of the possible operating conditions. Given that, as highlighted previously, the use is required of high voltage values on the bitlines BL and wordlines WL during the programming operations, these biasing steps may include, for example, pre-charging of one or more internal nodes and/or one or more of the main bitlines MBL to appropriate voltage values, higher than the same maximum withstandable voltage, exploiting for this purpose the presence of the protection elements MNC, MPC and the suitable biasing of the well-biasing terminal 18 in the programming decoding circuit 4b. It is thus possible to transfer the desired high voltage and the high driving current towards the selected memory cells 3, albeit with the use of just low-voltage transistors, thanks to the appropriate timing of the biasing steps, which cause the voltage differences involved in the circuit never to be higher than a maximum voltage withstandable by the same transistors.
For example, appropriate steps of pre-charging of the voltage on the main bitlines MBLp may be included, prior to selection of the local bitlines BL, as well as steps of boosting of the voltage on the control terminals of the protection elements MPC, in cascode configuration, and on the well-biasing terminal 18.
In general, for each of the operations of reading and programming of the SET and RESET states, suitable preliminary biasing steps may be included, such as to prevent subsequent stresses and overvoltages on the low-voltage transistors used in the decoding architecture 10, and moreover direct biasing of the junctions of the same transistors. These preliminary steps may include preparation of the main bitlines MBL (and corresponding pre-charging to appropriate boosted voltage values), and subsequently effective selection and biasing of the local bitlines BL and wordlines WL for access to the memory cells 3 involved in the programming operation. In particular, precharging and programming voltages are appropriately generated by a high-voltage booster circuit (not shown) of the memory device 1, for example including one or more charge pumps, and by appropriate partitions of the boosted voltage generated by the same booster circuit.
In general, the reading operations, for which the reading decoding circuit 4a of the column decoder 4 is involved, are less critical as regards the values of the electrical quantities involved, in particular the voltage values used and the consequent stresses for the low-voltage transistors.
In fact, reading operations do not require voltage values higher than the logic voltage Vdd. The presence of the protection element MNc also in the reading decoding circuit 4a is, however, advantageous, in so far as it protects the reading path from overvoltages generated during the programming operations.
In general, Table 1 below sums up possible voltage values in the decoding architecture 10 during operations of reading and programming of the SET or RESET states; V (well N) is the voltage present on the well-biasing terminal 18.
TABLE 1ProgrammingSignalReading(SET/RESET)V(well N)Vdd3.6 VYPVdd1.8 V (selected)3.6 V (not selected)MBLpVdd3.6 VYOPVdd1.8 V (selected)3.6 V (not selected)YPCGnd1.8 VBL0.4 V2.8 VYNCVdd1.8 VYONVddGndMBLr0.4 VGndYNVddGndWLVdd2.8 V
Based also on the values shown in Table 1, it may be noted that:
the use of boosted voltages may be required only during the operations of programming of the SET and RESET states (not during reading, where the voltages required do not exceed the logic voltage Vdd);
the first-level and second-level biasing units 19a, 20a of the reading decoding circuit 4a hence may not be critical aspects in design, and may include inverters of a traditional type capable of switching at output between the values Gnd and Vdd;
the first-level and second-level biasing units 19b, 20b of the programming decoding circuit 4b may require, instead, a specific design in order to supply at output four different voltage levels, namely: 0 V (Gnd), the logic voltage Vdd; the first pre-charging voltage Vpre1, in the example illustrated equal to 1.8 V; and the programming voltage Vp, in the example illustrated equal to 3.6 V;
likewise, the row-biasing unit 24 may be designed for supplying at output three different voltage levels, namely: 0 V (Gnd); the logic voltage Vdd; and the row-selection voltage Vrow, in the example illustrated equal to 2.8 V.
The above discussed architecture affords a considerable saving of area in the integrated implementation, due to the use of just low-voltage transistors; a considerable reduction of the current consumption; and a reduction of the complexity and costs of the manufacturing process, due to the reduction of the number of masks and implants required.